0
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--- uncomment the following library declaration if instantiating
--- any xilinx primitives in this code.
--library unisim;
--use unisim. vcomponents.all;
entity sonundasonu is
port ( aout : out std_logic;
bout : out std_logic;
pwm : out std_logic;
keyboard_clk : in std_logic;
keyboard_data : in std_logic;
clock_25mhz : in std_logic;
reset : in std_logic;
read1 : in std_logic;
scan_ready : out std_logic);
end sonundasonu;
architecture behavioral of sonundasonu is
signal xy : std_logic_vector(7 downto 0);
signal k,l,m,n : std_logic;
component ensonnn
port(
a : in std_logic;
b : in std_logic;
clk : in std_logic;
sag : in std_logic;
sol : in std_logic;
aout : out std_logic;
bout : out std_logic;
pwm : out std_logic
);
end component;
component kb
port(
keyboard_clk : in std_logic;
keyboard_data : in std_logic;
clock_25mhz : in std_logic;
reset : in std_logic;
read1 : in std_logic;
scan_code : out std_logic_vector(7 downto 0);
scan_ready : out std_logic
);
end component;
begin
inst_kb: kb port map(
keyboard_clk => keyboard_clk,
keyboard_data => keyboard_data ,
clock_25mhz => clock_25mhz,
reset => reset,
read1 => read1,
scan_code =>xy,
scan_ready =>scan_ready
);
inst_ensonnn: ensonnn port map(
a => k,
b => l,
aout => aout,
bout =>bout ,
clk => clock_25mhz,
pwm =>pwm ,
sag => m,
sol =>n
);
process(xy)
begin
if(xy="00011101") then
k<='1';
else
k<='0';
if(xy="00011011") then
l<='1';
else
l<='0';
if(xy="00011100") then
m<='1';
else
m<='0';
if(xy="00100011") then
n<='1';
else
n<='0';
end if;
end if;
end if;
end if;
end process;
end behavioral;
