herkes üniversiteli oldugunu kanıtlasın

şuraya 2 tane verilog kodu yazsam anlar mısınz binler dur yazıyorum aq.
After learning what the FIFO is, we started to write code for implementation;
`timescale 1ns / 1ps //one clock period
module fifo3( clk, idata, odata );
parameter boy = 10; //length of FIFO
input clk; //INPUTS
input [7:0] idata;
reg [10:0] addra = boy; //used variable in design
reg [10:0] addrb = 0;
reg [7:0] dina = 0;
output [7:0] odata; //OUTPUTS
wire wea = 1;
bellek inst( //call bellek block in our design
.addra (addra), //determine input and output ports
.addrb (addrb),
.clka (clk),
.clkb (clk),
.dina (idata),
.doutb (odata),
.wea (wea));
always@(negedge clk)begin //our design function part
addra <= addra + 1;
addrb <= addrb + 1;
end
endmodule